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Dual-Phase, Single or Dual Output Synchronous Step-Down Controller
POWER MANAGEMENT Description
The SC2446A is a high-frequency dual synchronous stepdown switching power supply controller. It provides outof-phase output gate signals. The SC2446A operates in synchronous continuous-conduction mode. Both phases are capable of maintaining regulation with sourcing or sinking load currents, making the SC2446A suitable for generating both VDDQ and the tracking VTT for DDR applications. The SC2446A employs fixed frequency peak currentmode control for the ease of frequency compensation and fast transient response. The dual-phase step-down controllers of the SC2446A can be configured to provide two individually controlled and regulated outputs or a single output with shared current in each phase. The Step-down controllers operate from an input of at least 4.7V and are capable of regulating outputs as low as 0.5V The step-down controllers in the SC2446A have the provision to sense inductor RDC voltage drop for current-mode control. This sensing scheme eliminates the need of the current-sense resistor and is more noise-immune than direct sensing of the high-side or the low-side MOSFET voltage. Precise current-sensing with sense resistor is optional. Individual soft-start and overload shutdown timer is included in each step-down controller. The SC2446A implements hiccup overload protection. In two-phase singleoutput configuration, the master timer controls the softstart and overload shutdown functions of both controllers.
SC2446A
Features
2-Phase synchronous continuous conduction mode for high efficiency step-down converters Out of phase operation for low input current ripples Output source and sink currents Fixed frequency peak current-mode control 50mV/-75mV maximum current sense voltage Inductive current-sensing for low-cost applications Optional resistor current-sensing for precise current-limit Dual outputs or 2-phase single output operation Excellent current sharing between individual phases Wide input voltage range: 4.7V to 16V Individual soft-start, overload shutdown and enable Duty cycle up to 88% 0.5V feedback voltage for low-voltage outputs External reference input for DDR applications Programmable frequency up to 1MHz per phase External synchronization Industrial temperature range 28-lead TSSOP lead free package. This product is fully WEEE and RoHS compliant
Applications
Telecommunication power supplies DDR memory power supplies Graphic power supplies Servers and base stations
Typical Application Circuit
V IN (1 2 V ) V IN G N D
C6 R 55 R 49 C7
VO1
1 VDDO L6 C 62 C 45 R 46 10 11 VO CB
U 10 VDDC
PVCC 13 C 68 26 25 R 53 0 24 22 27 BST1 GDH 1 BST2 GDH 2
23 19 20 C 67 13 VDDC
U9 VDDO VO 1 10 11 L5 C 65 R 14 C 23
VO2
C 74
VI VSSC
16 9
R 52 21 0
16 9
VI VSSC
CB
C 75
28 VSSO R 13
GD L1 PGND VPN 1 CS1+ CS1IN1COMP1 REF AGND R osc AVCC R EFOU T
GD L2
VSSO 28 R 50 R CS-5
In te gra te d M O S F E T /D rive r
R CS-6
VPN 2 CS2+ CS2IN2COMP2 REFIN VIN 2 SYNC SS1/EN 1 SS2/EN 2 U3
18 14 13 12 11 10 17 6 28 15 C 71 C 70 TP11 REF OUT (0. 5V) C 63 R 48
1 2 4 5
In te gra te d M O S F E T /D rive r
VO1GND
R 28 R 29 C 29 R 47 C 40 VIN C 72 C 73 R 45 REF OUT (0. 5V)
VO2GND
8 7 3 16 9
R 51 C 64
Figure 1
Revision: November 9, 2005
REF OUT (0. 5V)
SC2446A
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SC2446A
POWER MANAGEMENT Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device reliability.
Parameter Supply Voltage Gate Outputs GDH1, GDH2, GDL1, GDL2 voltages IN1-, IN2- Voltages REFOUT Voltages REF, REFIN Voltage COMP1, COMP2 Voltages CS1+, CS1-, CS2+ and CS2- Voltages SYNC Voltage SS1/EN1 AND SS2/EN2 Voltages Ambient Temperature Range Thermal Resistance Junction to Case (TSSOP-28) Thermal Resistance Junction to Ambient (TSSOP-28) Storage Temperature Range Lead Temperature (Soldering) 10 sec Maximum Junction Temperature
Symbol AVCC VGDH1, VGDH2,VGDL1, VGDL2 VIN1-,VIN2VREF ,VREFOUT VREFIN VCOMP1,VCOMP2 VCS1+,VCS1-,VCS2+,VCS2VSYNC VSS1,VSS2 TA J C J A TSTG TLEAD TJ
Maximum Ratings -0.3 to 16 -0.3 to 6 -0.3 to AVCC+0.3 -0.3 to 6 -0.3 to AVCC+0.3 -0.3 to AVCC+0.3 -0.3 to AVCC+0.3 -0.3 to AVCC+0.3 -0.3 to 6 -40 to 125 13 84 -60 to 150 260 150
Units V V V V V V V V V C C/W C/W C C C
Electrical Characteristics
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1k, -40C < TA = TJ < 125C
Parameter Undervoltage Lockout AVCC Start Threshold AVCC Start Hysteresis AVCC Operating Current AVCC Quiescent Current in UVLO Channel 1 Error Amplifier Input Common-Mode Voltage Range Inverting Input Voltage Range Input Offset Voltage Non-Inverting Input Bias Current Inverting Input Bias Current Amplifier Transconductance Amplifier Open-Loop Gain Amplifier Unity Gain Bandwidth Minimum COMP1 Switching Threshold
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Symbol
Conditions
Min
Typ
Max
Units
AVCCTH AVCCHYST ICC
AVCC Increasing
4.5 0.2
4.7
V V
AVCC= 12V AVCC = AVCCTH - 0.2V (Note 1) (Note 1) 0 ~ 70 C 0 0
8 2.5
15
mA mA
3 AVCC 1 -100 -100 260 65 5 3 -250 -250
V V mV nA nA -1 d MHz V
IREF IIN1GM1 aOL1
V C S 1+ = V C S 1- = 0 VSS1 Increasing
2
2.2
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SC2446A
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1k, -40C < TA = TJ < 125C
Parameter Amplifier Output Sink Current Amplifier Output Source Current Channel 2 Error Amplifier Input Common-mode Voltage Range Inverting Input Voltage Range Input Offset Voltage Non-inverting Input Bias Current Inverting Input Bias Current Inverting Input Voltage for 2-Phase Single Output Operation Amplifier Transconductance Amplifier Open-Loop Gain Amplifier Unity Gain Bandwidth Minimum COMP2 Switching Threshold Amplifier Output Sink Current Amplifier Output Source Current Oscillator Channel Frequency Synchronizing Frequency SYNC Input High Voltage SYNC Input Low Voltage SYNC Input Current Channel Maximum Duty Cycle Channel Minimum Duty Cycle Current-limit Comparators Input Common-Mode Range Cycle-by-cycle Peak Current Limit Valley Current Overload Shutdown Threshold Positive Current-Sense Input Bias Current Negative Current-Sense Input Bias Current
Symbol
Conditions VIN1- = 1V, VCOMP1 = 2.5V VIN1- = 0, VCOMP1 = 2.5V (Note 1) (Note 1) 0 ~ 70 C
Min
Typ 16 12
Max
Units A A
0 0 1.5 -150 -100 2.5
3 AVCC 3 -380 -250
V V mV nA nA V
IIN2+ IIN2-
GM2 aOL2 V C S 2+ = V C S 2- = 0 VSS2 Increasing VCOMP2 = 2.5V VCOMP2 = 2.5V fCH1, fCH2 0 ~ 70 C (Note 1) 450 2.1fCH 1.5
260 65 5 2.2 16 12 500 550
-1 d MHz V A A KHz KHz V 0.5 V A % 0 % V mV mV A A 1 50
ISYNC DMAX1, DMAX2 DMIN1, DMIN2
VSYNC = 0.2V VSYNC = 2V 88
0 VILIM1+, VILIM2+ VILIM1-, VILIM2ICS1+, ICS2+ ICS1-, ICS2VCS1- = VCS2- = 0.5V, Sourcing Mode, 0 ~ 70 C VCS1- = VCS2- = 0.5V, Sinking Mode, 0 ~ 70 C V C S 1+ = V C S 1- = 0 V C S 2- = V C S 2- = 0 V C S 1+ = V C S 1- = 0 V C S 2+ = V C S 2- = 0 40 -60 50 -75 -0.7 -0.7
AVCC - 1 60 -90 -2 -2
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SC2446A
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1k, -40C < TA = TJ < 125C
Parameter PWM Outputs Peak Source Current Peak Sink Current Output High Voltage Output Low Voltage Minimum On-Time
Symbol
Conditions
Min
Typ
Max
Units
GDL1, GDL2, GDH1, GDH2 GDL1, GDL2, GDH1, GDH2
AVCC = 12V AVCC = 12V Source IO = 1.2mA, 0 ~ 70 C Sink IO = 1mA TA = 25C 3.95 0
4 3 5 0.4 120
mA mA V V ns
Soft-Start, Overload Latchoff and Enable Soft-Start Charging Current Overload Latchoff Enabling Soft-Start Voltage Overload Latchoff IN1- Threshold Overload Latchoff IN2- Threshold Soft-Start Discharge Current Overload Latchoff Recovery Soft-Start Voltage PWM Output Disable SS/EN Voltage PWM Output Enable SS/EN Voltage Internal 0.5V Reference Buffer Output Voltage Load Regulation Line Regulation VREFOUT IREFOUT = -1mA, 0C < TA = TJ < 70C 0 < IREFOUT < -5mA AVCCTH < AVCC < 15V, IREFOUT = -1mA 495 500 0.05 0.02% 505 mV %/mA %V ISS1, ISS2 VSS1 = VSS2 = 1.5V VSS1 and VSS2 Increasing VSS1 = 3.8V, VIN1-Decreasing VSS2 = 3.8V, VIN2-Decreasing VIN1-= 0.5VREF, ISS1(DIS), ISS2(DIS) VIN2-= 0.5VREFIN , VSS1 = VSS2 = 3.8V VSSRCV1, VSSRCV2 VSS1 and VSS2 Decreasing 0.3 0.7 1.8 3.2 0.5VREF 0.5 X VREFIN 1.2 0.5 0.8 1.2 1.5 0.7 A V V V A V V V
Notes: (1) Guaranteed by design not tested in production. (2) This device is ESD sensitive. Use of standard ESD handling precautions is required.
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SC2446A
POWER MANAGEMENT Pin Configurations
TOP VIEW
CS1+ CS1ROSC IN1COMP1 SYNC AGND REF REFOUT REFIN COMP2 IN2CS2CS2+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SS1/EN1 VPN1 BST1 GDH1 GDL1 PVCC PGND GDL2 GDH2 BST2 VPN2 VIN2 AVCC SS2/EN2
Ordering Information
Device SC2446AITSTRT(1)(2) S C 2446A E V B P ackag e TSSOP-28 Evaluation Board Temp. Range( TA) -40 to 125C
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices for TSSOP package. (2) Lead free product. This product is fully WEEE and RoHS compliant.
(28 Pin TSSOP)
Figure 2
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SC2446A
POWER MANAGEMENT Pin Descriptions
TSSOP Package
Pin 1 2 3 4 5 6 7 8 9 10 11 12 Pin Name C S 1+ C S 1ROSC IN1COMP1 SYNC AGND REF REFOUT REFIN COMP2 IN2Pin Function The Non-inverting Input of the Current-sense Amplifier/Comparator for the Controller 1. The Inverting Input of the Current-sense Amplifier/Comparator for the Controller 1. Normally tied to the output of the converter. An external resistor connected from this pin to GND sets the oscillator frequency. Inverting Input of the Error Amplifier for the Step-down Controller 1. Tie an external resistive divider between OUTPUT1 and the ground for output voltage sensing. The Error Amplifier Output for Step-down Controller 1. This pin is used for loop compensation. Edge-triggered Synchronization Input. When not synchronized, tie this pin to a voltage above 1.5V or the ground. An external clock (frequency > frequency set with ROSC) at this pin synchronizes the controllers. Analog Signal Ground. The non-inverting input of the error amplifier for the step down converter 1. Buffered output of the internal reference voltage 0.5V. An external Reference voltage is applied to this pin.The non-inverting input of the error amplifier for the step-down converter 2 is internally connected to this pin. The Error Amplifier Output for Step-down Controller 2. This pin is used for loop compensation. Inverting Input of the Error Amplifier for the Step-down Controller 2. Tie an external resistive divider between output2 and the ground for output voltage sensing. Tie to AVCC for two-phase single output applications The Inverting Input of the Current-sense Amplifier/Comparator for the Controller 2. Normally tied to the output of the converter. The Non-inverting Input of the Current-sense Amplifier/Comparator for the Controller 2 An external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch off time for step-down converter 2. Pulling this pin below 0.7V shuts off the gate drivers for the second controller. Leave open for two-phase single output applications. Power Supply Voltage for the Analog Portion of the Controllers. No connection. No connection. No connection. PWM Output for the High-side N-channel MOSFET of Output 2.
13 14 15 16 17 18 19 20
C S 2C S 2+ SS2/EN2 AVCC VIN2 VPN2 BST2 GDH2
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SC2446A
POWER MANAGEMENT Pin Descriptions
Pin 21 22 23 24 25 26 27 28 Pin Name GDL2 PGND PVC C GDL1 GDH1 BST1 VPN1 SS1/EN1 Pin Function Logic Enable gate drive signal for Output 2. No connection. No connection. Logic Enable gate drive signal for Output 1. PWM Output for the High-side N-channel MOSFET of Output 1. No connection. No connection. An external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch off time for buck converter 1. Pulling this pin below 0.7V shuts off the gate drivers for the first controller.
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SC2446A
POWER MANAGEMENT Block Diagram
SYNC 6 ROSC 3 COMP1 5 IN14 REF 8 OSCILLATOR CLK FREQUENCY DIVIDER SLOPE COMP
CLK2 CLK1 1.25V REFERENCE
AVCC 16 BST1 26 0.5V GDH1 25 R S Q VPN1 27 UV GDL1 24
+
SLOPE2 EA1
SLOPE1
+
PWM1
CS1+ 1 CS12
+
-
ISEN1
+
+
+
Soft-Start And Overload Hiccup Control 1
OL1 DSBL1
PGND 22 SS1/EN1 28 VIN2 17
50mV 75mV REFOUT 9
-
ILIM1+ I OCN1
+ +
ILIM1 -
0.5 (REFOUT)
0.5V PVCC UVLO 4.3/4.5V 23
-
AGND 7 B A Y 0.5 (REFIN) SEL BST2 19 GDH2 20 R S Q VPN2 18 UV GDL2 21
COMP2 11
+
1.8V
+
SEL ANALOG SWITCH EA2
CLK2
IN212 REFIN 10
+
SLOPE2
+
PWM2
CS2+ 14 CS213
+
-
ISEN2
+
+
+
Soft-Start And Overload Hiccup Control 2
0.5 (REFIN)
OL2 DSBL2 SS2/EN2 15
50mV 75mV
-
ILIM2 I OCN2
+
ILIM2 -
Figure 3. SC2446A Block Diagram
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SC2446A
POWER MANAGEMENT Block Diagram
OCN
IN0.5(VREFOUT) / 0.5(VREFIN ) SS/EN
+ 1.8
S Q R 0.5V/3.2V OL
DSBL UVLO 0.8V/1.2V
3
Figure 4. Soft-Start and Overload Hiccup Control Circuit
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SC2446A
POWER MANAGEMENT Application Information
SC2446A consists of two current-mode synchronous buck controllers with many integrated functions. By proper application circuitry configuration, SC2446A can be used to generate 1) two independent outputs from a common input or two different inputs or 2) dual phase output with current sharing, 3) current sourcing/sinking from common or separate inputs as in DDR (I and II) memory application. The application information related to the converter design using SC2446A is described in the following. Step-down Converter Starting from the following step-down converter specifications, Input voltage range: Vin [ Vin,min , Vin,max ] Input voltage ripple (peak-to-peak): Vin Output voltage: Vo Output voltage accuracy: Output voltage ripple (peak-to-peak): Vo Nominal output (load) current: Io Maximum output current limit: Io,max Output (load) current transient slew rate: dIo (A/s) Circuit efficiency: Selection criteria and design procedures for the following are described. 1) output inductor (L) type and value, 2) output capacitor (Co) type and value, 3) input capacitor (Cin) type and value, 4) power MOSFET's, 5) current sensing and limiting circuit, 6) voltage sensing circuit, 7) loop compensation network. Operating Frequency (fs) The switching frequency in the SC2446A is userprogrammable. The advantages of using constant frequency operation are simple passive component selection and ease of feedback compensation. Before setting the operating frequency, the following trade-offs should be considered. 1) 2) 3) 4) 5) Passive component size Circuitry efficiency EMI condition Minimum switch on time and Maximum duty ratio
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For a given output power, the sizes of the passive components are inversely proportional to the switching frequency, whereas MOSFETs/Diodes switching losses are proportional to the operating frequency. Other issues such as heat dissipation, packaging and the cost issues are also to be considered. The frequency bands for signal transmission should be avoided because of EM interference. Minimum Switch On Time Consideration In the SC2446A the falling edge of the clock turns on the top MOSFET gate. The inductor current and the sensed voltage ramp up. After the sensed voltage crosses a threshold determined by the error amplifier output, the top MOSFET gate is turned off. The propagation delay time from the turn-on of the controlling FET to its turnoff is the minimum switch on time. The SC2446A has a minimum on time of about 120ns at room temperature. This is the shortest on interval of the controlling FET. The controller either does not turn on the top MOSFET at all or turns it on for at least 120ns. For a synchronous step-down converter, the operating duty cycle is VO/VIN. So the required on time for the top MOSFET is VO/(VINfs). If the frequency is set such that the required pulse width is less than 120ns, then the converter will start skipping cycles. Due to minimum on time limitation, simultaneously operating at very high switching frequency and very short duty cycle is not practical. If the voltage conversion ratio VO/VIN and hence the required duty cycle is higher, the switching frequency can be increased to reduce the sizes of passive components. There will not be enough modulation headroom if the on time is simply made equal to the minimum on time of the SC2446A. For ease of control, we recommend the required pulse width to be at least 1.5 times the minimum on time.
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SC2446A
POWER MANAGEMENT Application Information (Cont.)
Setting the Switching Frequency The switching frequency is set with an external resistor connected from Pin 3 to the ground. The set frequency is inversely proportional to the resistor value (Figure 5). The followings are to be considered when choosing inductors. a) Inductor core material: For high efficiency applications above 350KHz, ferrite, Kool-Mu and polypermalloy materials should be used. Low-cost powdered iron cores can be used for cost sensitive-applications below 350KHz but with attendant higher core losses. b) Select inductance value: Sometimes the calculated inductance value is not available off-the-shelf. The designer can choose the adjacent (larger) standard inductance value. The inductance varies with temperature and DC current. It is a good engineering practice to re-evaluate the resultant current ripple at the rated DC output current. c) Current rating: The saturation current of the inductor should be at least 1.5 times of the peak inductor current under all conditions. Output Capacitor (Co) and Vout Ripple Figure 5. Free running frequency vs. ROSC. Inductor (L) and Ripple Current Both step-down controllers in the SC2446A operate in synchronous continuous-conduction mode (CCM) regardless of the output load. The output inductor selection/design is based on the output DC and transient requirements. Both output current and voltage ripples are reduced with larger inductors but it takes longer to change the inductor current during load transients. Conversely smaller inductors results in lower DC copper losses but the AC core losses (flux swing) and the winding AC resistance losses are higher. A compromise is to choose the inductance such that peak-to-peak inductor ripple-current is 20% to 30% of the rated output load current. Assuming that the inductor current ripple (peak-to-peak) value is *Io, the inductance value will then be
L= Vo (1 - D) . Io fs
800 700 600 fs (kHz) 500 400 300 200 100 0 0 50 100 150 200 250 Rosc (k Ohm)
The output capacitor provides output current filtering in steady state and serves as a reservoir during load transient. The output capacitor can be modeled as an ideal capacitor in series with its parasitic ESR (Resr) and ESL (Lesl) (Figure 6).
Co
Lesl
Resr
Figure 6. An equivalent circuit of Co. If the current through the branch is ib(t), the voltage across the terminals will then be
di ( t ) 1 v o ( t ) = Vo + ib ( t )dt + L esl b + R esr ib ( t ). Co 0 dt
The peak current in the inductor becomes (1+/2)*Io and the RMS current is
IL,rms = Io 1 + 2 . 12
t
This basic equation illustrates the effect of ESR, ESL and Co on the output voltage. The first term is the DC voltage across Co at time t=0. The second term is the voltage variation caused by the
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SC2446A
POWER MANAGEMENT Application Information (Cont.)
charge balance between the load and the converter output. The third term is voltage ripple due to ESL and the fourth term is the voltage ripple due to ESR. The total output voltage ripple is then a vector sum of the last three terms. Since the inductor current is a triangular waveform with peak-to-peak value *Io, the ripple-voltage caused by inductor current ripples is
v C Io , 8C o fs
The voltage rating of aluminum capacitors should be at least 1.5Vo. The RMS current ripple rating should also be greater than
Io 23 .
Usually it is necessary to have several capacitors of the same type in parallel to satisfy the ESR requirement. The voltage ripple cause by the capacitor charge/discharge should be an order of magnitude smaller than the voltage ripple caused by the ESR. To guarantee this, the capacitance should satisfy
Co > 10 . 2fsR esr
the ripple-voltage due to ESL is
v ESL I = L esl fs o , D
and the ESR ripple-voltage is
v ESR = R esr Io .
Aluminum capacitors (e.g. electrolytic, solid OS-CON, POSCAP, tantalum) have high capacitances and low ESL's. The ESR has the dominant effect on the output ripple voltage. It is therefore very important to minimize the ESR. When determining the ESR value, both the steady state ripple-voltage and the dynamic load transient need to be considered. To keep the steady state output ripple-voltage < Vo, the ESR should satisfy
R esr1 < Vo . Io
In many applications, several low ESR ceramic capacitors are added in parallel with the aluminum capacitors in order to further reduce ESR and improve high frequency decoupling. Because the values of capacitance and ESR are usually different in ceramic and aluminum capacitors, the following remarks are made to clarify some practical issues. Remark 1: High frequency ceramic capacitors may not carry most of the ripple current. It also depends on the capacitor value. Only when the capacitor value is set properly, the effect of ceramic capacitor low ESR starts to be significant. For example, if a 10F, 4m ceramic capacitor is connected in parallel with 2x1500F, 90m electrolytic capacitors, the ripple current in the ceramic capacitor is only about 42% of the current in the electrolytic capacitors at the ripple frequency. If a 100F, 2m ceramic capacitor is used, the ripple current in the ceramic capacitor will be about 4.2 times of that in the electrolytic capacitors. When two 100F, 2m ceramic capacitors are used, the current ratio increases to 8.3. In this case most of the ripple current flows in the ceramic decoupling capacitor. The ESR of the ceramic capacitors will then determine the output ripple-voltage. Remark 2: The total equivalent capacitance of the filter bank is not simply the sum of all the paralleled capacitors. The total equivalent ESR is not simply the parallel combination of all the individual ESR's either. Instead they should be calculated using the following formulae.
To limit the dynamic output voltage overshoot/ undershoot within (say 3%) of the steady state output voltage) from no load to full load, the ESR value should satisfy
R esr 2 < Vo . Io
Then, the required ESR value of the output capacitors should be Resr = min{Resr1,Resr2 }.
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SC2446A
POWER MANAGEMENT Application Information (Cont.)
C eq () := (R1a + R1b )2 2C1a C1b + (C1a + C1b )2 (R1a C1a + R1b C1b )2 C1a C1b + (C1a + C1b ) R1aR1b (R1a + R1b )2C1a C1b + (R1b C1b + R1a C1a ) (R1a + R1b )2 2 C1a C1b + (C1a + C1b )2
2 2 2 2 2 2 2 2 2 2
R eq () :=
where R 1a and C 1a are the ESR and capacitance of electrolytic capacitors, and R1b and C1b are the ESR and capacitance of the ceramic capacitors respectively. (Figure 7)
Figure 8. A simple model for the converter input In Figure 8 the DC input voltage source has an internal impedance Rin and the input capacitor Cin has an ESR of Resr. MOSFET and input capacitor current waveforms, ESR voltage ripple and input voltage ripple are shown in Figure 9.
C1a
C1b
Ceq
R1a
R1b
Req
Figure 7. Equivalent RC branch. Req and Ceq are both functions of frequency. For rigorous design, the equivalent ESR should be evaluated at the ripple frequency for voltage ripple calculation when both ceramic and electrolytic capacitors are used. If R1a = R1b = R1 and C1a = C1b = C1, then Req and Ceq will be frequencyindependent and Req = 1/2 R1 and Ceq = 2C1. Input Capacitor (Cin) The input supply to the converter usually comes from a pre-regulator. Since the input supply is not ideal, input capacitors are needed to filter the current pulses at the switching frequency. A simple buck converter is shown in Figure 8. Figure 9. Typical waveforms at converter input. It can be seen that the current in the input capacitor pulses with high di/dt. Capacitors with low ESL should be used. It is also important to place the input capacitor close to the MOSFETs on the PC board to reduce trace inductances around the pulse current loop. The RMS value of the capacitor current is approximately
ICin = Io D[(1 + 2 D D )(1 - )2 + 2 (1 - D) ]. 12
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SC2446A
POWER MANAGEMENT Application Information (Cont.)
The power dissipated in the input capacitors is then PCin = ICin2Resr. For reliable operation, the maximum power dissipation in the capacitors should not result in more than 10oC of temperature rise. Many manufacturers specify the maximum allowable ripple current (ARMS) rating of the capacitor at a given ripple frequency and ambient temperature. The input capacitance should be high enough to handle the ripple current. For higher power applications, multiple capacitors are placed in parallel to increase the ripple current handling capability. Sometimes meeting tight input voltage ripple specifications may require the use of larger input capacitance. At full load, the peak-to-peak input voltage ripple due to the ESR is
v ESR = R esr (1 + )Io . 2
Let the duty ratio and output current of Channel 1 and Channel 2 be D1, D2 and Io1, Io2, respectively. If D1<0.5 and D2<0.5, then
ICin D1Io1 + D 2Io2 .
2 2
Choosing Power MOSFETs The power devices with integrated gate drivers such as PIP212, R2J20601NP, PIP202, PIP201 and IP2001, IP2002 are suitable for SC2446A application. Current Sensing Inductor current sensing is required for the current-mode control. Although the inductor current can be sensed with a precision resistor in series with the inductor, the lossless inductive current sense technique is used in the SC2446A. This technique has the advantages of 1) lossless current sensing, 2) lower cost compared to resistive sense 3) more accurate compared to the RDS(ON) sense The basic arrangement of the inductive current sense is shown in Figure 10. Where, RL is the equivalent series resistance of the output inductor. The added Rs and C s form a RC branch for inductor current sensing.
The peak-to-peak input voltage ripple due to the capacitor is
v C DIo , Cin fs
From these two expressions, CIN can be found to meet the input voltage ripple specification. In a multi-phase converter, channel interleaving can be used to reduce ripple. The two step-down channels of the SC2446A operate at 180 degrees from each other. If both stepdown channels in the SC2446A are connected in parallel, both the input and the output RMS currents will be reduced. Ripple cancellation effect of interleaving allows the use of smaller input capacitors. When converter outputs are connected in parallel and interleaved, smaller inductors and capacitors can be used for each channel. The total output ripple-voltage remains unchanged. Smaller inductors speeds up output load transient. When two channels with a common input are interleaved, the total DC input current is simply the sum of the individual DC input currents. The combined input current waveform depends on duty ratio and the output current waveform. Assuming that the output current ripple is small, the following formula can be used to estimate the RMS value of the ripple current in the input capacitor.
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Vin
Q1 iL(t) Cin L Rs Q2 vC(t) RL Cs
Vo
Cout Rload
Figure 10. The basic structure of inductive current sense. In steady state, the DC value, VCS = RL IO
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SC2446A
POWER MANAGEMENT Application Information (Cont.)
It is noted that the DC value of VCs is independent of the value of L, Rs and Cs. This means that, if only the average load current information is needed (such as in average current mode control), this current sensing method is effective without time constant matching requirement. In the current mode control as implemented in SC2446A, the voltage ripple on Cs is critical for PWM operation. In fact, the AC voltage ripple peak-to-peak value of VCs (denoted as VCs) directly effects the signal-to-noise ratio of the PWM operation. In general, smaller VCs leads to lower signal-to-noise ratio and more noise sensitive operation. Larger VCs leads to more circuit (power stage) parameter sensitive operation. A good engineering compromise is to make VCs~ RL Io. The pre-requisite for such relation is the so called time constant matching condition when the load is sourcing current from the converter and
ILMcn = - 75mV , RL
when the load is forcing current back to the input power source. If RL = 1.8m, then ILM = 27.8 / -41.7A. The circuit in Figure 11 allows the user to scale the equivalent current limit with the same RL. In the following design steps, the capacitor CS in the current sensing part is commonly selected in the range of 22nF ~ 100nF.
Vin
Q1 Vgs1 iL(t) PN Cin Rs Q2 Vgs2 vC(t) Rs1 L RL
L R s Cs . RL
For an example of application circuit, L = 1H, RL = 1.8m, the time constant RsCs should be set as 555.6s. If one selects Cs = 33nF, then Rs = 16.9 k. Scaling the Current Limit
Vo
Cs Cout Rload
+ ISEN -
1 2
Rs2 Rs3
Over-current is handled differently in the SC2446A depending on the direction of the inductor current. If the differential sense voltage between CS+ and CS- exceeds +50mV, the top MOSFET will be turned off and the bottom MOSFET will be turned on to limit the inductor current. This +50mV is the cycle-by-cycle peak current limit when the load is drawing current from the converter. There is no cycle-by-cycle current limit when the inductor current flows in the reverse direction. If the voltage between CS1+ and CS- falls below -75mV, the controller will undergo overload shutdown and time-out with both the top and the bottom MOSFETs shut off. (See the section Overload Protection and Hiccup). In the circuit of Figure 11, the equivalent inductor current limits are set according to
ILMcp = 50mV , RL
Figure 11. Scaling the equivalent current limit. a) When the required current limit value ILM is greater than ILMcp, one just needs to remove Rs3, and solve the following equations
(R s // R s1 ) Cs = L , RL
ILMRL
R s1 = 50mV, R s + R s1
and for
R s 2 = R s // R s1 . R s ,R s1 and R s 2 .
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SC2446A
POWER MANAGEMENT Application Information (Cont.)
Note that RS2 is selected as RS//RS1 in order to reduce the bias current effect of the current amplifier in SC2446A. b) When the required current limit ILM is less than ILMcp, one just needs to remove Rs1 and solve
R sCs = L , RL
a) The time taken to discharge the capacitor from 3.2V to 0.5V
t ssf = C32 (3.2 - 0.5)V . 1.2A
If C32 = 0.1F, tssf is calculated as 225ms. b) The soft start time from 0.5V to 3.2V
t ssr = C32 (3.2 - 0.5)V . 1.8A
ILMRL +
Rs VO = 50mV, R s3
for Rs and RS3. Rs2 is then obtained from
R s2 = R s 3R s . R s3 - R s
When C32 = 0.1F, tssr is calculated as 150ms. Note that during soft start, the converter only starts switching when the voltage at SS/EN exceeds 1.2V. c) The effective start-up time is
t sso = C32 (3.2 - 1.2)V . 1.8A
Similar steps and equations apply to the current limit setting and scaling for current sinking mode. Overload Protection and Hiccup During start-up, the capacitor from the SS/EN pin to ground functions as a soft-start capacitor. After the converter starts and enters regulation, the same capacitor operates as an overload shutoff timing capacitor. As the load current increases, the cycle-bycycle current-limit comparator will first limit the inductor current. Further increase in loading will cause the output voltage (hence the feedback voltage) to fall. If the feedback voltage falls to less than (50% for Ch1, 50% for Ch2) of the reference voltage, the controller will shut off both the top and the bottom MOSFETs. Meanwhile an internal net 1.2A current source discharges the softstart capacitor C32(C33) connected to the SS/EN pin. When the capacitor is discharged to 0.5V, a 1.8A current source recharges the SS/EN capacitor and converter restarts. If overload persists, the controller will shut down the converter when the soft start capacitor voltage exceeds 3.2V. The converter will repeatedly start and shut off until it is no longer overloaded. This hiccup mode of overload protection is a form of foldback current limiting. The following calculations estimate the average inductor current when the converter output is shorted to the ground.
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The average inductor current is then
ILeff = ILMcp t sso . t ssf + t ssr
ILeff 0.30 ILMcp and is independent of the soft start capacitor value. The converter will not overheat in hiccup. Setting the Output Voltage The non-inverting input of the channel-one error amplifier is internally tied the 0.5V voltage reference output (Pin 8). The non-inverting input of the channel-two error amplifier is brought out as a device pin (Pin 10) to which the user can connect Pin 8 or an external voltage reference. A simple voltage divider (Ro1 at top and Ro2 at bottom) sets the converter output voltage. The voltage feedback gain h=0.5/Vo is related to the divider resistors value as
Ro2 = h R o1. 1- h
Once either R o1 or R o2 is chosen, the other can be calculated for the desired output voltage Vo. Since the number of standard resistance values is limited, the calculated resistance may not be available as a standard value resistor. As a result, there will be a set error in the
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SC2446A
POWER MANAGEMENT Application Information (Cont.)
converter output voltage. This non-random error is caused by the feedback voltage divider ratio. It cannot be corrected by the feedback loop. The following table lists a few standard resistor combinations for realizing some commonly used output voltages. The inner current-loop is unstable (sub-harmonic oscillation) unless the inductor current up-slope is steeper than the inductor current down-slope. For stable operation above 50% duty-cycle, a compensation ramp is added to the sensed-current. In the SC2446A the compensation ramp is made duty-ratio dependent. The compensation ramp is approximately
Iramp = De1.76D * 30A.
Vo (V) (1- h)/h 0.6 0.2 0.9 0.8 806 1K 1.2 1.4 1.4K 1K 1.5 2 2K 1K 1.8 2.6 2.5 4 3.3 5.6
The slope of the compensation ramp is then
S e = (1 + 1.76D)e1.76D fs * 30A.
Ro1 (Ohm) 200 Ro2 (Ohm) 1K
2.61K 4.02K 5.62K 1K 1K 1K
Only the voltages in boldface can be precisely set with standard 1% resistors. From this table, one may also observe that when the value
1 - h Vo - 0.5 = h 0.5
The slope of the internal compensation ramp is well above the minimal slope requirement for current loop stability and is sufficient for all the applications. With the inner current loop stable, the output voltage is then regulated with the outer voltage feedback loop. A simplified equivalent circuit model of the synchronous Buck converter with current mode control is shown in Figure 12.
and its multiples fall into the standard resistor value chart (1%, 5% or so), it is possible to use standard value resistors to exactly set up the required output voltage value. The input bias current of the error amplifier also causes an error in setting the output voltage. The maximum inverting input bias currents of error amplifiers 1 and 2 is -250nA. Since the non-inverting input is biased to 0.5V, the percentage error in the second output voltage will be -100% * (0.25A) * R R /[0.5 * (R +R ) ]. To keep o1 o2 o1 o2 this error below 0.2%, R < 4k. o2 Loop Compensation SC2446A uses current-mode control for both step-down channels. Current-mode control is a dual-loop control system in which the inductor peak current is loosely controlled by the inner current-loop. The higher gain outer loop regulates the output voltage. Since the current loop makes the inductor appear as a current source, the complex high-Q poles of the output LC networks is split into a dominant pole determined by the output capacitor and the load resistance and a high frequency pole. This pole-splitting property of current-mode control greatly simplifies loop compensation.
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k
Figure 12. A simple model of synchronous buck converter with current mode control. The transconductance error amplifier (in the SC2446A) has a gain gm of 260A/V. The target of the compensation design is to select the compensation network consisting of C2, C3 and R2, along with the feedback resistors Ro1,
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SC2446A
POWER MANAGEMENT Application Information (Cont.)
Ro2 and the current sensing gain, such that the converter output voltage is regulated with satisfactory dynamic performance. With the output voltage Vo known, the feedback gain h and the feedback resistor values are determined using the equations given in the "Output Voltage Setting" section with
h= 0.5 . Vo
The loop transfer function is then T(s)=Gvc(s)C(s). To simplify design, we assume that C3<C2 = gmhkR o , 2fc R oCo , C2
For the rated output current Io, the current sensing gain k is first estimated as
k= Io . 2.1
R2 =
From the transfer function from the voltage error amplifier output vc to the converter output vo is
Vo (s) := G vc (s) = kR o Vc (s) s s z1 . s 1+ s p1 1+
and
C3 = R oesr C o K, R2
where, the single dominant pole is
s p1 = 1 , (R o + R oesr )C o
with a constant K. For example, if Vo=2.5V, Io=15A, fs=300kHz, Co=1.68mF, Roesr=4.67m, one can calculate that
Ro = Vo = 167m, Io 0.5 = 0.2, Vo
and the zero due to the output capacitor ESR is
s z1 = 1 R oesr C o .
h=
and
k= Io = 7.14. 2.1
The dominant pole moves as output load varies. The controller transfer function (from the converter output vo to the voltage error amplifier output vc) is
s s z2 gm h , C(s) = s s(C 2 + C 3 ) 1+ sp2 1+
If the converter crossover frequency is set around 1/10 of the switching frequency, fc = 30kHz, the controller parameters then can be calculated as
C2 = gmhkR o 0.328nF. 2fc
where
s z2 = 1 , R 2C2
where, gm is the error amplifier transconductance gain (260 -1). If we use C2 = 0.33 nF,
R2 = R oCo 848 .5k, C2
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and
sp2 = 1 . C 2C 3 R2 C 2 + C3
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SC2446A
POWER MANAGEMENT Application Information (Cont.)
use R2 = 770k. With K = 1, it is further calculated that
C3 = R oesr C o K 10.2pF, R2
It is clear that the resulted crossover frequency is about 27.1 kHz with phase margin 91o. It is noted that the current sensing gain k was first estimated using the DC value in order to quickly get the compensation parameter value. When the circuit is operational and stable, one can further improve the compensation parameter value using AC current sensing gain. One simple and practical method is to effectively measure the output current at two points, e.g. Io1 and Io2 and the corresponding error amplifier output voltage Vc1 and Vc2. Then, the first order AC gain is
use C3 = 10pF. The Bode plot of the loop transfer function (magnitude and phase) is shown in Figure 13
69.241
100
50 20 log G vc( f ) C( f )
(
)
0
k=
Io I -I = o1 o 2 Vc Vc1 - Vc 2
With this k value, one can further calculate the improved compensator parameter value using the previous equations.
10 10 100 1 .10
3
- 20.73 50
f
1 .10
4
1 .10
5
1 .10 3x10
5
6
For example, if one measured that Io1=1A, Io2=15A and Vc1=2.139V, Vc2=2.457V. k is then calculated as 44. Substituting this parameter to the equations before, one can derive that C2 2.024nF. Select C2 = 2.2nF. R2 127.3k. Select R2 = 127k. C3 61.78pF. Select C3 = 47pF In some initial prototypes, if the circuit noise makes the control loop jittering, it is suggested to use a bigger C3 value than the calculated one here. Effectively, the converter bandwidth is reduced in order to reject some high frequency noises. In the final working circuit, the loop transfer function should be measured using network analyzer and compared with the design to ensure circuit stability under different line and load conditions. The load transient response behavior is further tested and measured to meet the specification.
f - 88.78 88 89 90 91 92 - 92.702 93 10 10 100
arg G vc( f) C( f)
(
)
180
1 .10
3
f
1 .10
4
1 .10
5
1 .10 3x10
5
6
Figure 13. The loop transfer function Bode plot of the example.
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SC2446A
POWER MANAGEMENT Application Information (Cont.)
PC Board Layout Issues Circuit board layout is very important for the proper operation of high frequency switching power converters. A power ground plane is required to reduce ground bounces. The followings are suggested for proper layout. Power Stage 1) Separate the power ground from the signal ground. In SC2446A, the power ground PGND should be tied to the source terminal of lower MOSFETs. The signal ground AGND should be tied to the negative terminal of the output capacitor. 2) Minimize the size of high pulse current loop. Keep the top MOSFET, bottom MOSFET and the input capacitors within a small area with short and wide traces. In addition to the aluminum energy storage capacitors, add multilayer ceramic (MLC) capacitors from the input to the power ground to improve high frequency bypass. Control Section 3) The frequency-setting resistor Rosc should be placed close to Pin 3. Trace length from this resistor to the analog ground should be minimized. 4) Solder the bias decoupling capacitor right across the AVCC and analog ground AGND. 5) Place the Combi-sense components away from the power circuit and close to the corresponding CS+ and CS- pins. Use X7R type ceramic capacitor for the Combisense capacitor because of their temperature stability. 6) Use an isolated local ground plane for the controller and tie it to the negative side of output capacitor bank.
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TP16
VIN (12V)
VINGND
TP17
POWER MANAGEMENT Typical Application Schematic
C7 10uF 10uF 10uF C19 C18 PVC C 26 BST1 GDH1 0 VO C39 100nF CBP 5 2.2nF R14 2.2 VSSO 22 PIP212 VPN 2 CS2+ CS2IN2COMP2 REFIN VIN2 SY NC SS1/EN1 SS2/EN2 U1 28 15 TP6 C33 0.1uF C32 0.1uF 6 17 TP9 TP8 10 C45 0.1uF C36 33pF 11 TP13 R21 12.4K C37 12 13 R15 1.0M 14 18 42 56 VI VSSC 24 GDL1 1 PGND VPN 1 CS1+ CS1IN1COMP1 REF AGND Rosc AVC C REFOUT GD L2 TP10 22 27 1 2 4 5 TP12 R19 12.4K C28 3 16 9 33pF 10 C35 1uF 0.1uF C34 R26 49.9K C31 6.8nF R20 C29 0.1uF 7 8 R8 10K 21 55 DISABLE GD H2 20 R7 VDDO 11 BST2 4 VDDC 25 R31 0 19 1uF U6 10 TP1 L2 1uH C15 C20 100nF R5 20K C49 23 R24 U5 11 VDDO 42 VO VI TP11 R10 10K VSSC PIP212 1 56 5 CBP 22 VSSO DISABLE 55 VDDC 4 1uF 10uF R23 10 TP2 10uF 10uF
C5
C4
C3
C6
C2
C9
C10
10uF 10uF
VO1 (2.5V, 15A)
TP3
VO2 (1.2V, 15A)
TP4
L1 1uH C38 100nF R6 20K C48 R13 2.2
C46
C22
C24
C30
C21 100nF C14 2.2nF
C27 100uF
C25 10uF
C26 100uF
C47 100uF
100uF 10uF
100uF
100uF
21
22pF R9 2.2M
RC S+1 49.9K
22pF
TP14
RCS-1 20K
RC S-2 20K TP15 C44 1uF R12 10K
VO1GND
R11
C43 1uF
VO2GND
10K
R17 6.8nF 7.15K
R16
2.49K
SC2446A
Vin=12V
SC2446A
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SC2446A
POWER MANAGEMENT Typical Characteristics
S C 2 4 4 6 A + P I P 2 1 2 D u a l P ha s e E ffi c ie n c y V i n = 1 2 V , D u a l O u tp u t, F s w = 5 0 0 K H z, Ta m b = 2 5 C , 0 L F M
1 0.98 0.96 0.94 0.92 0.9 0.88 E f fic ien c 0.86 0.84 0.82 0.8 0.78 0.76 0.74 0.72 0.7 2 4 6 8 10 12 AMP S 14 15 16 18 20
Channel 1: Vo1 = 2.5V Channel 2: Vo2 = 1.2V
2. 5V Ef fic i en c y 1. 2V Ef fic i en c y
D ua l P h a s e Th e rm a l s V i n = 1 2 V , D u a l O utp u t, F s w = 5 0 0 K H z, T a m b = 2 5 C , 0 LF M
70
60
50 Te m p e r a t u r e ( d e
40
30
2. 5V 1. 2V 2. 5V 1. 2V
t h erm t h erm t h erm t h erm
als als als als
20
10
0 0 2 4 6 8 10 A M PS 12 14 16 18 20
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SC2446A
POWER MANAGEMENT Typical Characteristics (Cont.)
Ch1 (2.5V) Output voltage ripple = 14.0mV p-p
Ch2 (1.2V) Output voltage ripple = 15.6mV p-p
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SC2446A
POWER MANAGEMENT Typical Characteristics (Cont.)
Ch1 (2.5V) Full load start-up
Vin = 12V Io1 Vout1 = 2.5V
Ch1 (2.5V) Shutdown
Vin = 12V
Vout1 = 2.5V
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SC2446A
POWER MANAGEMENT Typical Characteristics (Cont.)
Ch2 (1.2V) Full load start-up
Vin = 12V Io2 Vout2 = 1.2V
Ch2 (1.2V) Shutdown
Vin = 12V
Vout2 = 1.2V
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SC2446A
POWER MANAGEMENT Typical Characteristics (Cont.)
Vin = 12V, Dual output, Fsw = 500KHz, Tamb = 25 C, 0LFM 2.5V Output short and release.
VO2
VO1
IO1
Vin = 12V, Dual output, Fsw = 500KHz, Tamb = 25 C, 0LFM 1.2V Output short and release.
VO1
VO2
IO2
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SC2446A
POWER MANAGEMENT Outline Drawing - TSSOP-28
A e N 2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123 E D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.047 .002 .006 .031 .042 .007 .012 .003 .007 .378 .382 .386 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 28 0 8 .004 .004 .008 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 9.60 9.70 9.80 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 28 0 8 0.10 0.10 0.20
e/2 B D A2 A
aaa C SEATING PLANE
C
bxN bbb
A1 C A-B D GAGE PLANE 0.25
H c
L (L1) DETAIL
01
SIDE VIEW
SEE DETAIL
A
A
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AE.
Land Pattern - TSSOP-28
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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